1. Field of the Invention
The present invention relates to a code sequence generator and to a method of generating a code sequence.
2. Description of Related Art
In third generation (3G) and other telecommunications systems, it is commonplace for a transmitted signal to be “spread” across a wide frequency range to improve the signal to noise plus interference ratio of the transmitted signal. As part of this spreading process, a pseudo-random bit sequence known as a scrambling code may be applied to the signal to be transmitted. One approach to generating the scrambling code to be applied to the signal to be transmitted is to use a linear feedback shift register (LFSR). An LFSR is shown generally at 10 in FIG. 1, and comprises a shift register 12 which is pre-loaded with an initial bit sequence (known as a seed), a feedback logic network 14 and an output logic network 16.
The feedback logic network 14 is typically a network of one or more exclusive-or logic gates whose inputs are connected to particular elements of the shift register 12. The feedback logic network 14 generates a new input bit, which is input to the shift register 12 at the most significant bit (MSB) position. The output logic network 16 is typically a network of exclusive-or gates whose inputs are connected to particular elements of the shift register 12.
The LFSR 10 is clocked, such that each clock cycle the contents of the shift register 12 are shifted to the right by one position. The feedback logic network 14 causes a new bit value to be input to the MSB position of the shift register 12 each clock cycle, and this changes the contents of the shift register 12. The output logic network 16 generates an output bit each clock cycle, which output bit is dependent upon the contents of the elements of the shift register 12 to which the inputs of the output logic network cycle are connected. In this way, a pseudo-random bit sequence is output by the LFSR 10 over the course of a number of clock cycles.
A disadvantage of the LFSR illustrated in FIG. 1 is that only one bit of the output bit sequence (i.e. the code generated) is produced each clock cycle, and thus it may take a considerable amount of time to generate a scrambling code, which in turn delays “downstream” operations.